1. Field of the Invention
The invention relates to a method of fabricating a dual-damascene copper structure, and more particularly, to a method of fabricating a dual-damascene copper structure through an atomic chemical vapor deposition (CVD) process to form a barrier layer.
2. Description of the Prior Art
With the increasing complexity of integrated circuits, the multilevel interconnect process has become the typical method used in semiconductor integrated circuit fabrication. To satisfy the requirements for high integration and high speed in integrated circuits (ICs), especially in a deep sub-micro (<0.18 μm) semiconductor process, a copper (Cu) dual damascene process is becoming more widely used as a standard process in forming an interconnection line within the inter-metal dielectric layer of low dielectric constant (low k) materials. Since copper has both a low resistance and a low electromigration resistance, the low k materials are useful in improving the RC delay effect of a metal interconnection.
Please refer to FIG. 1, which is a cross-sectional view of a semiconductor wafer 10 with a typical dual-damascene copper structure 11. As shown in FIG. 1, the dual-damascene copper structure 11 formed within a dielectric layer 20 comprises a dual-damascene hole 21 and conductive materials filled in the dual-damascene hole 21. The dual-damascene hole 21 is composed of a via 22 and a trench 23. An underlying metal wire 14 is formed in a dielectric layer 12 beneath the via 22. A Cu conductive layer or a upper metal wire 24 fills the trench 23 and is electrically connected with the underlying metal wire 14 by the via plug 22a and through the dielectric layer 12, the dielectric layer 20, and the passivation layer 18. In addition, the dual-damascene copper structure 11 can be used for electrically connecting the electric device on the silicon substrate of the semiconductor wafer 10 and upper metal wires, while the via plug directly contacts the surface of the silicon substrate.
To avoid diffusion of copper atoms from the dual-damascene copper structure 11 to the adjacent dielectric layer 20 resulting in current leakages, a barrier layer 25 is generally formed on the surface of the dual-damascene hole 21 before filling copper in the dual-damascene hole 21. A suitable material used to form the barrier layer 25 must possess the following requirements: (1) ability to block copper atoms, (2) good adhesion to Cu and the dielectric layer, (3) low resistance, and (4) good step coverage. Therefore, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc. are typically used to form the barrier layer. As a result, to form a barrier layer that can effectively prevent copper atoms from diffusing is one of the important keys for the dual-damascene copper structure.
In the prior art, U.S. Pat. No. 6,403,465 entitled “Method to Improve Copper Barrier Properties” discloses a method of fabricating a dual-damascene copper structure with improved barrier layer. The patent teaches a method comprising performing an in-situ physical vapor deposition (PVD) process or chemical vapor deposition (CVD) to form a barrier layer in the dual-damascene hole along with an ion-metal-plasma (IMP) deposition to form an adhesion layer before filling the copper layer in the dual-damascene hole so that a combined adhesion/barrier layer is formed in the surface of the dual-damascene hole. In this prior art, the barrier layer is composed of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, or titanium silicon nitride. After forming the barrier layer, a metal seed layer is formed in the dual-damascene hole for forming a copper layer.
However, as the integration of chips increases, the prior-art technology for fabricating the dual-damascene copper structures causes some problems. Especially when the line width is less than 65 nanometers (nm), the barrier layer formed through the conventional PVD or CVD process has bad step coverage ability and bad conformance, resulting in bad performance of preventing copper atoms from diffusing. For instance, the titanium nitride layer formed through a conventional PVD process serving as a barrier layer cannot block copper atoms diffusing effectively, and that results in current leakages. Furthermore, when the conventional barrier layer does not have good conformance, the problem that the barrier layer and copper layer cannot fully fill the dual-damascene hole may occur, which also causes defects of via plugs. For solving these problems, manufacturers have researched and designed an atomic CVD process to form a tantalum nitride layer that has better ability for blocking copper atoms when serving as a barrier layer. However, when the dual-damascene copper structure is fabricated directly on a silicon substrate, the precursor of the atomic CVD process for forming the tantalum nitride layer causes damage of the silicon substrate or defects of electric devices on the silicon substrate. In addition, the seed layer of coppers has bad adhesion ability to the tantalum nitride layer formed through the atomic CVD process so as to influence the following processes of forming the copper layer and other devices.